This invention relates generally to operational amplifiers and in particular to CMOS operational amplifiers, and is more particularly directed toward a multi-stage integrator having high gain and fast transient response.
An op amp (operational amplifier) architecture is desirable which is suited to current and foreseeable future generations of small geometry CMOS (complementary metal-oxide-semiconductor), manufactured economically in high volume using the same processes as those used for manufacturing digital circuitry.
The conventional op amp, illustrated in FIG. 1 in block diagram form, and generally depicted by the numeral 100, comprises two gain stages. The first functions as a differential transconductance (gm) stage 101 and the second as an integrator 103, separated by a differential to single-ended converter 102. The conventional op amp 100 is illustrated in more detail in FIG. 2.
As shown in FIG. 2, the gm stage 101 comprises a differential pair 201, 202 with a single current source xe2x80x9ctailxe2x80x9d 203 (both typically, and as an example, p-type insulated-gate field effect transistors), and two current source loads 204, 205 (typically, and as an example, provided by n-type transistors). By selecting an output 206 from only one of the differential input stages, differential to single-ended conversion is accomplished or, conventionally, current sources 204 and 205 are implemented as a mirror with single-ended output 206 derived from the high impedance side of the mirror.
This single-ended output 206 is then applied to the integrator stage 103. In the implementation shown, the integrator 103 includes a n-type output transistor 207 with a current source tail 210, and Miller capacitor 208. A nulling resistor 209 has been added for the sake of stability.
In sub-micron CMOS technology, it is difficult to achieve an integrator with a combination of high gain and wide bandwidth with a high slew rate and a good transient response to high frequency events. The active devices are fast, but a single gain stage has very low DC gain. This may be increased by techniques such as cascading, but to a limited extent; also, deep sub-micron processes have very restricted supply voltages which make it desirable to use the full voltage range efficiently without cascoding. A multi-stage integrator (typically three inverting gains) gives high gain with simple inverters, but must be stabilized with an internal nested pole, which sharply degrades the bandwidth and thus results in a poor slew rate and poor transient response.
Consequently, a need arises for an integrator implementation that provides high gain and good transient response, while offering simplicity of design and economy in overall circuit area.
These needs and others are satisfied by the present invention, in which a three-stage integrator achieves a high small-signal gain on the order of 80 dB, with 200 MHz typical bandwidth, and very clean transient pulse response. Only simple inverters are used, making the design scalable to deep sub-micron with low supply voltages, a rail-to-rail output swing, and a relatively low output impedance and useful tolerance to capacitive loading.
In accordance with one aspect of the invention, a high-gain, fast response amplifier comprises a first amplifier path including a plurality of inverters and a first amplifier path output, a second amplifier path having a common input with the first amplifier path, and including a transconductor and a second amplifier path output, and a resistor interconnecting the first and second amplifier paths to form a composite amplifier having the common input as the input thereto and the output of the second amplifier path as the output thereof.
The first amplifier path may include first and second cascaded inverters coupled to an output stage, while the second cascaded inverter may include a compensation network connected in feedback to improve stability. The compensation network may be a series RC network. In a preferred form of the invention, the amplifier further comprises a capacitor connected in feedback around the first amplifier path. The resistor interconnecting the first and second amplifier paths preferably has a conductance g equal to the transconductance gm of the transconductor.
In accordance with a further aspect of the present invention, a method is provided for minimizing high-frequency transient signals at an amplifier output. The method comprises the steps of providing an amplifier having an amplifier input and amplifier output, feeding back a sample of high frequency output signals from the amplifier output to the amplifier input, providing a secondary signal path having a common input with the amplifier input, and adding the secondary signal path output to the amplifier output to effectively remove the high-frequency transient signals.
In accordance with yet another aspect of the present invention, an integrator comprises a first signal path including multiple cascaded inverting amplifiers coupled between the integrator input and an amplifier output, a second signal path limited to a single transconductor coupled between integrator input and output, a resistor coupled between the amplifier output and the integrator output, and a capacitor coupled between the amplifier output and the integrator input. The first signal path provides a relatively high-gain, narrowband amplifier, and the second signal path provides a relatively low-gain, broadband amplifier, and the first and second signal paths sum through the resistor to form a single amplifying structure with relatively high low-frequency gain, and relatively fast high-frequency transient response.